As is well-known in the art, output buffers are commonly used with a variety of electronic and computer type integrated circuits. Specifically, the output buffer circuit provides, when enabled, an output signal which is a function of a data input signal from other logic circuitry of the integrated circuit.
Output buffer circuits typically use a pull-up transistor device and a pull-down transistor device connected in series between first and second power supply terminals. The first power supply terminal may be supplied with a positive potential VCC, which is connected to an internal power supply potential node. A second power supply terminal may be supplied with a ground potential, which is connected to an internal ground potential node. The connection point of the pull-up and pull-down transistors is further joined to an output terminal. The output terminal is used for driving other circuitry on other integrated circuits which may have widely varying capacitive loading effects.
When a data input signal is transmitted through the integrated circuit, there is a certain amount of time delay for the data input signal to travel through the integrated circuit before it arrives at the output terminal as an output signal. The time delay is commonly known as propagation delay. In smaller integrated circuits where the propagation delay through the circuit is very short, the propagation delay due to the output buffer represents a high percentage of the propagation delay for the entire integrated circuit. Thus a great deal of effort has been expended over the years to reduce the output buffer propagation delay in order to speed up the performance of smaller integrated circuits.
Furthermore, depending upon the logic state of the data input signal and an enable signal, either the pull-up or the pull-down transistor is quickly turned ON and the other is turned OFF. Such rapid ON and OFF switching of the pull-up and pull-down transistor devices causes sudden surges of current creating what is commonly known as current spikes. Also, during output switching, charging and discharging currents from the pull-up and pull-down transistors to the external capacitance load exist. These transient current (current spikes and charging/discharging currents) will flow through the impedance and inductive components of power supply and ground lines so as to cause noises at the internal power supply potential and the internal ground potential nodes of the output buffer. The noise at the internal ground potential is undesirable because it will degrade the logic "1" and logic "0" voltage levels which are commonly used in digital circuits, causing interfacing problems among the output buffer circuit and other integrated circuits. The undesirable ground noise is generally referred to as "ground bounce". The ground bounce will be more severe when more output buffers are switching simultaneously, at higher operating speed, or driving larger external capacitance loads.
In the design of output buffer circuits, it is thus seen that a trade-off exists between achieving high-speed/high-drive operation and minimizing of the ground bounce. As the demand for higher speed circuits dominates more and more in the market place, output buffers are found to be either unacceptable in speed performance or are too noisy to be used practically. Accordingly, there has been a long-felt but unsatisfied need to provide output buffer circuits which operate at high speed and yet minimize ground bounce.
In addition, during the rapid ON and OFF switching of the pull-up and pull-down transistor, there exists a condition in which the pull-up transistor remains ON temporarily as it is being turned OFF while the pull-down transistor is being turned ON. This causes a sudden surge of current flowing from VCC through the pull-up and pull-down transistor to ground, creating what is commonly known as crowbar current. A parameter which is commonly used for measurement of power in a CMOS integrated circuit chip is the dynamic current, commonly known as ICC, which is the average sum of all the switching current from the internal and output buffers at a specific frequency. The crowbar current in the output buffer is part of the switching current and contributes a significant percentage to the ICC. Hence high crowbar current will cause high dynamic ICC, and accordingly, an undesirably high total power consumption of the integrated circuit chip.
Attempts have been made previously to achieve higher speed and higher output drive currents when the data input changes from a high logic level to a low logic level by increasing the sizes of the output pull-down transistor. However, it is known that large transistors have large gate capacitance which increase propagation delay. In order to minimize the adverse effect of large gate capacitance in large transistors, the transistors must be buffered by additional buffers, such as inverter gates. Such additional buffers will increase the delay time which may offset the reduction of delay time due to the increase in size of the transistors. As a result, the overall improvement in propagation delay by simply increasing the size of the output pull-down transistor is minimal. Further, increasing the size of the output pull-down transistor results in the disadvantage of increasing the ground bounce due to the increase in the amount of current flowing through a larger transistor. In other words, in order to minimize the ground bounce for the prior art output buffer circuit design, the high-speed or high-drive needs to be sacrificed. In addition, these solutions do not address the problems associated with crowbar current.
Accordingly, what is needed is an output buffer circuit that is flexible and is simple to implement. What is also needed, is an output buffer circuit which reduces the propagation delay associated with previously known output buffer circuits when the data input signal changes from a high logic level to a low logic level, while at the same time does not increase the ground bounce. Finally, what is needed is an output buffer circuit which minimizes crowbar current and hence power consumption.
The present invention provides an output buffer circuit which minimizes the propagation delay of the output buffer circuit when the data input signal changes from a high logic level to a low logic level, while maintaining the ground bounce at an acceptable level. The output buffer circuit also includes means for minimizing crowbar current when the data input signal changes from a high logic level to a low logic level.